# Secret Decoders

I’ve been a bit lazy giving updates but I did spend some time working out an overall design for the instruction set I outlined last time. Getting close on that, but for today I’ll go over some new circuit components that should be useful.

A few posts ago I described demultiplexers, which can be used to direct an input value to one of its ‘n’ output lines. A decoder is quite similar, except instead of passing an input value through a decoder simply selects (sets to 1) one of its ‘n’ outputs based on its inputs.

For example, consider the 2:4 decoder (2 input lines, selecting one of 4 output lines) above. When A1 is high (1) and A0 is low (0) then line X2 is selected (2 is 10 in binary; A1=1 and A0=0).

Similarly, the other combinations of A1 and A0 select their corresponding output line:

A1 | A0 | 1 | 0 |
---|---|---|---|

0 | 0 | X0 | all others |

0 | 1 | X1 | all others |

1 | 0 | X2 | all others |

1 | 1 | X3 | all others |

Here’s how it all works. Take a close look at the table above and note the combination of 0’s and 1’s for the A1 and A0 input lines. If both A1 and A0 are low (0) then X0 is high (1), if A1 is low (0) and A0 is high (1) then X1 is high (1), and so on.

The 2:4 decoder circuit emulates this logic table using a series of AND and NOT gates to combine its two input lines (A1 and A0) accordingly.

An AND gate (the semi-circular symbols in the circuit above) outputs high (1) only if both of its inputs are also high otherwise it outputs low (0). A NOT gate (triangles in the circuit above) outputs the “opposite” of its input (e.g. high to low, low to high).

Let’s look at the X2 example again. According to the table above, X2 is selected (high) only when A1=1 and A0=0. However we can’t simply AND the two input values (e.g. “A1 AND A0”) because we’d get “1 AND 0” which results in 0. Not the quite result we’re looking for.

The key here is the A0=0 part. What we really want is “1 AND 1” but only when A0 is 0. That’s where the NOT comes into play…NOT 0 = 1!

This allows us to express our desired “1 AND 1” as “1 AND (NOT 0)”; or in terms of our input lines “A1 AND (NOT A0)”. The only way that expression is true (1) is if A1 = 1 and A0=0. If you don’t believe me, the table below might help ðŸ™‚

Output | A1 | A0 | NOT A0 | A1 AND (NOT A0) | Value |
---|---|---|---|---|---|

X0 | 0 | 0 | 1 | 0 AND 1 | 0 |

X1 | 0 | 1 | 0 | 0 AND 0 | 0 |

X2 | 1 | 0 | 1 | 1 AND 1 | 1 |

X3 | 1 | 1 | 0 | 1 AND 0 | 0 |

There’s a whole world of boolean logic (or boolean algebra) available to us to play games like this ðŸ™‚ We’ll probably use a few more tricks like this in future circuits too.

Following through with this, the remaining output lines can be determined using similar boolean logic:

Output | A1 | A0 | Logic |
---|---|---|---|

X0 | 0 | 0 | (NOT A1) AND (NOT A0) |

X1 | 0 | 1 | (NOT A1) and A0 |

X2 | 1 | 0 | A1 AND (NOT A0) |

X3 | 1 | 1 | A1 AND A0 |

I’ll leave it up to you to figure out how these are all wired into that 2:4 decoder circuit diagram ðŸ™‚

By combining multiple AND and NOT gates it’s possible to create 3:8, 4:16, etc. decoders. Since I’m pretty sure I’ll need at least the 3:8 and 4:16 decoders I wired some up:

You probably noticed that I cheated a bit ðŸ™‚

Rather than creating a large number of AND and NOT gates I instead used a lower order decoder (e.g. a 2:4 for the 3:8 and a 3:8 for the 4:16) along with a 2-output demultiplexer.

The decoder handles the “lower most” input lines (e.g. the lower 2 of 3 inputs, or the lower 3 or 4 inputs) while the demultiplexer handles the “upper most” input line by redirecting decoder’s outputs to either the lower or upper ‘n’ output lines (e.g. the lower/upper 4 outputs, or the lower/upper 8 outputs).

Well, I just realized that I didn’t really give any examples on what a decoder can be used for! It’s getting late though so trust me, they’re useful ðŸ™‚